1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a system LSI having a debug function.
2. Description of the Background Art
A semiconductor device forming a predetermined system by a combination of a plurality of integrated circuits (modules) having various functions, that is, a system LSI stores software (a program) and hardware (for example, a hard-wired logic) which define an operation thereof. Whether or not the software and the hardware have errors is checked by a debugging operation which is important to a process of developing and manufacturing the system LSI.
FIG. 7 shows a general structure of the system LSI. The system LSI shown in FIG. 7 comprises a CPU (central processing unit) 1, a first processor 2, a second processor 3, an IO (input-output) processor 4 and a memory 5. These modules are connected through a bus line 6, and receive and send a signal therebetween.
An example of the operation of the system LSI will be described below. Data input from the outside is stored in the memory 5 through the IO processor 4. The CPU 1, the first processor 2 and the second processor 3 exchange the input data through the memory 5, perform predetermined processings and finally output the processed data to the outside.
Since the CPU 1, the first processor 2 and the second processor 3 perform processings for the input data at the same time, they operate independently and are mutually synchronized with each other if necessary. For example, in a case where a program stored in the CPU 1 is debugged in such an operating situation, the operation of the CPU 1 is stopped to interrupt a special program for debugging into the CPU 1 and to check the operating state. In this case, it is also necessary to stop the operations of the first processor 2, the second processor 3 and the IO processor 4. For this reason, a stop signal SS is sent from the CPU 1 to these modules.
In the conventional system LSI, thus, an operation of each module is simply stopped in response to the stop signal sent from the CPU 1 simultaneously with the suspension of the operation of the CPU 1. Therefore, the conventional system LSI cannot deal with complicated debug patterns. As described above, each module operates independently. For this reason, it is hard to stop their operations at the same time. The conventional system LSI has not had a structure in which the outside is caused to know whether or not the operations of the first and second processors 2 and 3 are also stopped when the program stored in the CPU 1 is stopped. Therefore, if a program for debugging is input from a microcomputer provided on the outside or the like in order to execute the debugging for the program stored in the CPU 1 in a state in which the first and second processors 2 and 3 continue the operations, the first and second processors 2 and 3 are sometimes broken (on a software or hardware basis).
For example, even if the program stored in the CPU 1 is stopped in a predetermined specific portion to stop the operations of the first and second processors 2 and 3, the operations of the first and second processors 2 and 3 are not stopped immediately but after a predetermined time has passed because they are not generally stopped before a predetermined processing is completed. Accordingly, there have been the following problems. It is impossible to know internal states of the first and second processors 2 and 3 immediately after the operation of the CPU 1 is stopped. Even if the first and second processors 2 and 3 are reactivated to give data or an operation instruction from the CPU 1, the internal states of the first and second processors 2 and 3 progress more than those obtained immediately after the operation of the CPU 1 is stopped so that the first and second processors 2 and 3 are not ready to accept the data or operation instruction. Therefore, they ignore the data or operation instruction sent from the CPU 1 to continue a wrong operation or to cause hang-up. However, each module has not had a structure to eliminate such drawbacks.